1. Field of the Invention
The present invention relates generally to integrated circuits, more particularly, to a field effect transistor with asymmetric drain and source regions for enhanced performance of the field effect transistor especially within a memory cell.
2. Description of the Related Art
A field effect transistor such as a MOSFET (metal oxide semiconductor field effect transistor) is commonly used for many integrated circuits. For example, in a DRAM (dynamic random access memory) cell, a source or drain region of an access MOSFET has a pad disposed thereon with such a pad being coupled to a charge storage node of a charge storage capacitor. The pad is disposed onto substantially the whole area of the source or drain region for efficient charge transfer between the MOSFET and the charge storage node.
In the prior art, the source and drain regions each have a LDD (lightly doped drain) area toward the channel region. Such a LDD area creates a gently-sloped dopant profile between a source or drain region and the channel region. Thus, the LDD area reduces intensities of electric fields and thus undesired short channel effects in the MOSFET. However, such a LDD area limits efficient charge transfer between the MOSFET and the charge storage node of the charge storage capacitor, especially as the device size of the MOSFET is further scaled down.
U.S. Pat. No. 6,596,594 to Jyh-Chyurn Guo (hereafter referred to as “Guo”) discloses a method for fabricating a field effect transistor (FET) with an asymmetric channel region and asymmetric source and drain regions using five implantation steps. In Guo, the drain region has an implantation mask formed thereon for preventing implantation of dopant therein during some of the five implantation steps such that the source region has higher doping. Unfortunately, Guo has increased production cost with so many implantation steps.
Nevertheless, forming an asymmetric field effect transistor with higher doping in one of the drain and source regions is desired for enhanced performance of the field effect transistor.